The I2C bus is based on a very simple protocol, a small set of rules that dictate how the two lines SDA and SCL are supposed to operate to allow the transfer of data.
With the premise that, at idle, both lines are high (pull up):
Rule 1) During the transfer of a bit, the SDA line can change status only when the SCL line is low.
Rule 2) When the SCL line is high, the SDA line status indicates the value of a bit.
Two exceptions to the above rules create special conditions that are used to delimit the beginning and end of each “transaction” between two devices on the bus.
A START condition is indicated when (in violation of rule 1) the SDA line changes from high to low while SCL is high.
A STOP condition is indicated when (again in violation of rule 1) the SDA line changes from low to high while SCL is high.
The figure below extracted from a typical device datasheet is worth a million words.
The fact that I2C is a bus, instead of just a point to point connection, means that on the same two wires multiple devices might try (at different times) to talk to each other.
To identify devices on the bus, 7-bit device addresses were used originally, but the standard got eventually expanded with a 10-bit option bringing from 128 to 1024 the number of individual devices that can be theoretically connected and addressed on the bus.
Since this is a synchronous serial protocol, two distinct types of devices can access the network: Masters and Slaves. Masters can initiate the communication, they get to control the SCL line as they are in charge of the clock generation. They send commands and control the actual transfer speed. Slaves cannot initiate transactions, but they have to keep quiet and wait for a Master to provide the clock and when addressed, respond to the given command. Two Masters can initiate the communication at the same time and generate what is called a “bus collision”. Collisions are easy to detect: when one of the two devices is trying to send a “1” bit (SDA line in pull up) and he notices that “somebody else” is yanking the line low… there is the clue! Arbitration is a matter of deciding who gets to continue (the one sending the “0” wins…).
I2C Serial EEPROMs
As we said before though, 99% of I2C applications in embedded control rotate around a much simple scenario, where there is only one Master (the microcontroller) and one or a handful of slaves, so you don’t have to worry about collisions.
Also the most common type of slave devices used are, of course, the serial EEPROMS. If 25xxyyy is the numbering standard for all SPI capable serial EEPROMs, the 24xxyyy numbering scheme is used to identify the I2C capable memories.
I2C has been for years the favorite choice for Serial EEPROM users and manufacturers for two reasons:
- Only two pins (I/Os) are required to communicate with the device, enabling the embedded control designer to use very low pin count (read inexpensive) microcontrollers.
- Just four pads (areas of contacts on the chip) are required for a Serial EEPROM device, two for the power supply and the two lines. This reduces the silicon area overhead due to the contacts on a typically very small device (hence the high impact/cost of the pads) an important advantage in the eyes of the manufacturer.
In practice most I2C Serial EEPROMs have at least a fifth contact/pin (WP) to protect the device contents by disabling writing. I2C Serial EEPROMs are offered today in a five pin SOT23 package (this is the package typical used for individual “transistors” in surface mount technology) with capacities from 128 bits up to 16k bit (2k bytes)!
Further several Serial EEPROM models offer at least three additional pins (bringing the grand total to 8 ) , acting as address select inputs, to allow for banking of multiple devices (up to 8 ) on the same bus.
In fact, the original I2C specifications called for the 7 device address bits to be split in two groups:
- the first four bits (most significant) are fixed and assigned by the standard for each “type” of device: Serial EEPROMs were assigned the value “0101” for example.
- the remaining three bits (least significant) can be controlled with three external pins.
As a consequence, in any given I2C bus , the original standard would allow only up to 8 serial memory devices to coexist at the addresses: 0x50, 0x51… 0x57.
When the device is made to fit into a package with less than 8 pins (and in other special cases we will discuss below) the 3 least significant bits of the device address are hard-wired to ground internally (24LC00) or simply re-used of “other purposes” (24LC16B).
(to be continued)
