Optimizing the graphic library

While working on the porting to the PIC32 of the code developed for the original PIC24 book it occurred to me that there were some obvious optimizations I had yet to explore.

For a starter, the graphic.c library was using several resources including Timer3, the Output Compare 3 module, the Output Compare 4 module and the SPI1 port in addition to one general purpose I/O (RG0 in this case). The OC3 module was used to generate the Horizontal Synchronization pulse portion of the composite video signal, but the module output pin RD2 (active as soon as the module is enabled) was not used. Rather RG0 was “manually” set during the OC3 interrupt service routine and reset during the Timer3 interrupt service routine. This added unnecessary overhead to the application as the OC3 module could easily be configured to do it all by itself…

In fact, if instead of configuring the OC3 module to perform single pulses we have it configured for continuous mode (OC3CON=0x000d), we can now remove completely the corresponding interrupt service routine and simplify the code inside the Timer3 ISR so to vary the duration of the pulses as needed to perform a vertical sync (long) pulse or an horizontal sync (short) pulse.

Optimized graphic.c module

The code simplification is only one of the benefits:

  • one general purpose I/O (RG0) pin can now be freed,
  • the continuous operation of OC3 assures an even more accurate and glitch-less horizontal sync timing, and most importantly
  • a number of cycles has been shaved off from the graphic module total overhead.

The main disadvantage is that now we need to modify the circuit assembled in the prototyping area (or the AV16 board, if you got the PCB or the kit…). The HSYNC signal must now be connected to the RD2 pin.

Looking at the simulation plots (obtained with the Logic Analyzer tool) and comparing the results with what published in chapter 12 of the book, you will see a further reduction of approximately 20 cycles out of 200 we used to count (a 10% relative improvement).

Logica Analyzer Plot

But the main limitation of the profiling technique used (setting an I/O each time we enter an ISR) makes us underestimate the benefits of this simple optimization. In fact, by omitting completely the OC3 ISR, we have eliminated a few more cycles required to the PIC24 to enter and exit the interrupt– 6 to be more precise.

Finally since we are talking about optimizations, let’s not forget that the MPLAB C30 compiler v3.02 Student Edition allows optimization level 1 to be used even after the initial 60 days period!

By using the -O1 compiler switch (or simply opening the Project Options dialog box with Project>Build Options>Project, selecting the MPLAB C30 pane, selecting Optimizations in the Categories combo box, and finally selecting Level 1 ) and recompiling we can get a significantly more compact code and a total cycle count of just 100 cycles. That is, the graphic module offers now only half the overhead of the previous revision!

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